Business Wire

DVCon Europe “Must See”: Aldec Tutorial and Demonstration on Adopting Easier UVM to Enable FPGA-Based Acceleration

MUNICH--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is supporting the second Annual DVCon Europe ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
Business Wire

Agnisys Offers Free Register Generator for UVM

SAN JOSE, Calif.--(BUSINESS WIRE)--Agnisys today announced a free version of its Hardware Specification tool – IDesignSpec™. It enables users to capture hardware specification that is automatically ...
Design-Reuse

Cadence Boosts Verification Productivity for Complex FPGA/ASIC Design

SAN JOSE, Calif. -- Jan 10, 2011 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a global leader in electronic design innovation, today announced significant new advancements to help boost ...
New Electronics

Aldec: Verification tool takes fpga/asic debugging to next level

Aldec has launched the latest version of its Riviera-Pro high performance, mixed signal language verification tool, which it claims takes fpga and asic debugging to the next level. According to the ...
EDN

Getting in sync with UVM sequences

The SystemVerilog universal verification methodology (UVM) is an efficient way to generate tests and check results for functional verification, best used for block level IC or FPGA or other “smaller” ...
Design-Reuse

Mentor Graphics Adds Memory Models to Create Industry's First Complete UVM SystemVerilog Verification IP Library

WILSONVILLE, Ore., Feb. 29, 2016 – Mentor Graphics Corporation (NASDAQ: MENT) today announced availability of the first entirely native UVM SystemVerilog memory verification IP library for all ...
Business Wire

Aldec HES-7 with Xilinx Virtex UltraScale Devices Enables True FPGA-based Verification

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is extending its leadership in ...
Semiconductor Engineering

Trends In FPGA Verification Effort And Adoption: The 2018 Wilson Research Group Functional Verification Study

As contributors and pioneers in the digital revolution, we are often so busy creating and innovating that we are compelled to focus on the trees, never mind the forest. But as we are all aware, the ...
Semiconductor Engineering

The Next Big Shift In Verification

We are coming to the end of the year—have you started your Christmas shopping list yet? For us bloggers, it is time for predictions about what the next year will bring in EDA technology. Three core ...