Semiconductor Engineering

Stress-Related Local Layout Effects In FinFET Technology And Device Design Sensitivity

“Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close proximity ...
Semiconductor Engineering

Automatic Layout Generator Targeting Region-based Layouts for Advanced FinFET-Based Full-Custom Circuits (UT Austin/NVIDIA)

A technical paper titled “AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies” was published by researchers at UT Austin and NVIDIA. “This paper presents AutoCRAFT, an ...
Business Wire

Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support Down to 5nm, and Simulation-Driven Layout

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ: CDNS) today introduced major enhancements to its Cadence ® Virtuoso ® custom IC design platform that improve electronic system ...
Business Insider

UMC and Synopsys Collaboration Speeds 14-nm Custom Design

MOUNTAIN VIEW, Calif. and HSINCHU, Taiwan, March 14, 2017 /PRNewswire/ -- Highlights: Custom Compiler support brings visually-assisted automation to UMC customers New industry-standard interoperable ...
EDN

IMEC set to report on improved FinFETs

LONDON — European nanoelectronics research institute IMEC (Leuven, Belgium) is expected to report on its work improving FinFETs at somewhere close to the 25-nanometer process node at the forthcoming ...